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preliminary rev. 0.4 10/12 copyright ? 2012 by silicon laboratories SI53303 this information applies to a product under dev elopment. its characteristics and specifications are s ubject to change without n otice. SI53303 d ual 1:5 l ow j itter b uffer /l evel t ranslator features applications description the SI53303 is an ultra low jitter dual 1:5 differential output buffer with pin- selectable output clock signal format and divider selection. the SI53303 utilizes silicon laboratories' adva nced cmos technology to fanout clocks from 1 to 725 mhz with guaranteed low additive jitter, low skew, and low propagation delay variability. the SI53303 features minimal cross-talk and provides superior supply noise rejection, simplifying low jitter clock distribution in noisy environments. independent core and output bank supply pi ns provide integrated level translation without the need for external circuitry. functional block diagram ? 10 differential or 20 lvcmos outputs ? ultra-low additive jitter: 100 fs rms ? wide frequency range: 1 to 725 mhz ? any-format input with pin selectable output formats: lvpecl, low power lvpecl, lvds, cml, hcsl, lvcmos ? synchronous output enable ? output clock division: /1, /2, /4 ? low output-output skew: <50 ps ? low propagation delay variation: <400 ps ? independent v dd and v ddo : 1.8/2.5/3.3 v ? excellent power supply noise rejection (psrr) ? selectable lvcmos drive strength to tailor jitter and emi performance ? small size: 44-qfn (7 mm x 7 mm) ? rohs compliant, pb-free ? industrial temperature range: ?40 to +85 c ? high-speed clock distribution ? ethernet switch/router ? optical transport network (otn) ? sonet/sdh ? pci express gen 1/2/3 ? storage ? telecom ? industrial ? servers ? backplane clock distribution v ref diva divb power supply filtering vref generator v ddob oe b sfout b [1:0] q0, q1, q2, q3, q4 q0, q1, q2, q3, q4 oe a v ddoa sfout a [1:0] div a div b clk0 clk0 clk1 clk1 q5, q6, q7, q8, q9 q5, q6, q7, q8, q9 patents pending ordering information: see page 25. pin assignments SI53303 gnd pad 27 26 25 24 23 29 28 30 32 31 33 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 7 8 9 10 11 5 6 4 2 3 1 nc nc nc clk0 clk0 clk1 clk1 v ref v ddoa q0 q0 q1 q1 q2 q2 q3 q3 q4 q4 gnd v ddob q5 oea q5 q6 q6 q7 q7 q8 q8 q9 q9 gnd diva sfouta[1] sfouta[0] oeb divb sfoutb[1] sfoutb[0] gnd v dd nc nc
SI53303 2 preliminary rev. 0.4 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 2. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 2.1. universal, any-format i nput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2. input bias resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3. universal, any-format output buff er . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.4. synchronous output enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.5. flexible output divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.6. output enable lo gic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.7. power supply (v dd and v ddox ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.8. output clock terminati on options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 2.9. ac timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.10. typical phase noise performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.11. input noise isolati on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.12. power supply noise rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3. pin description: 44-pin qfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5. package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.1. 7x7 mm 44-qfn package di agram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6. pcb land pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 6.1. 7x7 mm 44-qfn package land pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7. top marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.1. SI53303 top marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.2. top marking explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
SI53303 preliminary rev. 0.4 3 1. electrical specifications table 1. recommended operating conditions parameter symbol test condition min typ max unit ambient operating temperature t a ?40 ? 85 c supply voltage range* v dd lvds, cml, hcsl, lvcmos 1.71 1.8 1.89 v lvpecl, low power lvpecl, lvds, cml, hcsl, lvcmos 2.38 2.5 2.63 v 2.97 3.3 3.63 v output buffer supply voltage* v ddo lvds, cml, hcsl, lvcmos 1.71 ? 1.89 v lvpecl, low power lvpecl, lvds, cml, hcsl, lvcmos 2.38 ? 2.63 v 2.97 ? 3.63 v *note: core supply vdd and output buffer supplies v ddo are independent. table 2. input clock specifications (v dd =1.8v ? 5%, 2.5 v ? 5%, or 3.3 v ? 10%, t a = ?40 to 85 c) parameter symbol test condition min typ max unit differential input common mode voltage v cm vdd=2.5v ? 5%, 3.3v ? 10% 0.05 ? ? v input swing (single-ended, peak-to- peak) v in 0.1 ? 1.1 v input voltage high v ih vdd x 0.7 ? ? v input voltage low v il ? ? vdd x 0.3 v input capacitance c in ?5?pf
SI53303 4 preliminary rev. 0.4 table 3. dc common characteristics (v dd =1.8v ?? 5% , 2.5 v ? 5%, or 3.3 v ?? 10%,t a = ?40 to 85 ? c ) parameter symbol test condition min typ max unit supply current i dd ?tbd100ma output buffer supply current (per clock output) @100 mhz i ddox lvpecl (3.3 v) ? 35 ? ma low power lvpecl (3.3 v) ? 30 ? ma lvds (3.3 v) ? 20 ? ma cml (3.3 v) ? 30 ? ma hcsl, 100 mhz, 2 pf load (3.3 v) ? 35 ? ma cmos (1.8 v, sfout = open/0), per output, c l =5pf, 200mhz ?5?ma cmos (2.5 v, sfout=open/0), per output, c l =5pf, 200 mhz ?8?ma cmos (3.3 v, sfout = 0/1), per output, c l =5pf, 200mhz ?15?ma leakage current i l input leakage at all inputs except clkin, v in =0v ??tbda input leakage at clkin v in =0v ??tbda voltage reference v ref v ref pin ? vdd/2 ? v input high voltage v ih sfoutx, divx 3-level input pins 0.85 x vdd ??v input mid voltage v im sfoutx, divx 3-level input pins 0.45 x vdd 0.5 x vdd 0.55 x vdd v input low voltage v il sfoutx, divxpin 3-level input pins ? ? 0.15 x vdd v internal pull-down resistor r down clk_sel, diva, divb, sfouta[1], sfoutb[1] ?25?k ? internal pull-up resistor r up sfouta[1], sfoutb[1], diva, divb, oea, oeb ?25?k ?
SI53303 preliminary rev. 0.4 5 table 4. dc characteristics?lvpecl and low power lvpecl (v dd = 2.5 v ? 5%, or 3.3 v ?? 10%,t a = ?40 to 85 ? c ) parameter symbol test condition min typ max unit output voltage high v oh r l =50 ? to v ddox ? 2 v v ddox ? 1.145 ?v ddox ? 0.895 v output voltage low v ol r l =50 ? to v ddox ? 2 v v ddox ? 1.945 ?v ddox ? 1.695 v output dc common mode voltage v com v ddox ? 1.895 ?v ddox ? 1.425 v single-ended output swing v se terminate unused outputs to r l =50 ? to v ddox ? 2 v 0.25 0.60 0.85 v table 5. dc characteristics?cml (v dd =1.8v ?? 5% , 2.5 v ? 5%, or 3.3 v ?? 10%,t a = ?40 to 85 ? c ) parameter symbol test condition min typ max unit single-ended output swing v se terminated as shown in figure 7 (cml termination). 300 400 500 mv table 6. dc characteristics?lvds (v dd =1.8v ?? 5% , 2.5 v ? 5%, or 3.3 v ?? 10%,t a = ?40 to 85 ? c ) parameter symbol test condition min typ max unit single-ended output swing v se r l =100 ? across q n and q n 247 ? 454 mv output common mode voltage (v ddo =2.5v or 3.3 v) v com1 v ddox = 2.38 to 2.63 v, 2.97 to 3.63 v, r l =100 ? across q n and q n 1.10 1.25 1.35 v output common mode voltage (v ddo =1.8v) v com2 v ddox = 1.71 to 1.89 v, r l =100 ? across q n and q n 0.85 0.97 1.10 v
SI53303 6 preliminary rev. 0.4 table 7. dc characteristics?lvcmos (v dd =1.8v ?? 5% , 2.5 v ? 5%, or 3.3 v ?? 10%,t a = ?40 to 85 ? c ) parameter symbol test condition min typ max unit output voltage high * v oh 0.8 x v ddox ?? v output voltage low * v ol ??0.2 x v ddox v *note: i oh and i ol per the output signal format table for specific v ddox and sfoutx settings. table 8. dc characteristics?hcsl (v dd =1.8v ?? 5% , 2.5 v ? 5%, or 3.3 v ?? 10%,t a = ?40 to 85 ? c ) parameter symbol test condition min typ max unit output voltage high v oh r l =50 ? to gnd 550 700 850 mv output voltage low v ol r l =50 ? to gnd ?150 0 150 mv single-ended output swing v se r l =50 ? to gnd ? 700 ? mv crossing voltage v c r l =50 ? to gnd 250 350 550 mv
SI53303 preliminary rev. 0.4 7 table 9. ac characteristics (v dd =1.8v ?? 5% , 2.5 v ? 5%, or 3.3 v ?? 10%,t a = ?40 to 85 ? c ) parameter symbol test condition min typ max unit frequency f lvpecl, low power lvpecl, lvds, cml, hcsl 1?725mhz lvcmos 1 ? 200 mhz duty cycle note: 50% input duty cycle. d c 200 mhz, 50 ?? to ? v dd /2 ?? 20/80% ? t r /t f <10% of period (lvcmos) tbd tbd tbd % 20/80% t r /t f <10% of period (differential) 48 50 52 % minimum input clock slew rate 1 sr required to meet prop delay and additive jitter specifications (20-80%) 0.75 ? ? v/ns output rise/fall time t r /t f lvpecl, lvds, cml, hcsl, 20/80% 350 ps 200 mhz, 50 ??? 20/80%, 2 pf load (lvcmos) tbd tbd 750 ps minimum input pulse width t w 500 ? ? ps additive jitter (differential clock input) jv dd = 2.5/3.3 v, lvpecl/lvds, f = 725 mhz, 0.75 v/ns input slew rate ?6080fs propagation delay t plh, t phl low to high, high to low single-ended tbd ? tbd ns low to high, high to low differential tbd ? tbd ns output enable time 2 t en f=1mhz ? 2 ? ? s f = 100 mhz ? 60 ? ns f = 725 mhz ? 50 ? ns output disable time 2 t dis f=1mhz ? 2 ? ? s f = 100 mhz ? 25 ? ns f = 725 mhz ? 15 ? ns notes: 1. for clock division applications, a minimum input clock slew rate of 30 mv/ns is required. 2. see figure 4. 3. defined as skew between outputs on different devices operati ng at the same supply voltages, temperatures, and equal load conditions. using the same type of inputs on each devi ce, the outputs are measured at the differential cross points. 4. measured for 156.25 mhz carrier frequency. sine-wave noise added to v ddox (1.8v=50mv pp , 2.5/3.3v=100mv pp ) and noise spur amplitude measured. see an491 for further details.
SI53303 8 preliminary rev. 0.4 output to output skew t sk identical configuration, single- ended (q n to q m ) ??100ps identical configuration, differen- tial (q n to q m ) ??50ps part to part skew 3 t ps identical configuration ? 50 ? ps power supply noise rejection 4 psrr 10 khz sinusoidal noise ? ?90 ? dbc 100 khz sinusoidal noise ? ?90 ? dbc 500 khz sinusoidal noise ? ?80 ? dbc 1 mhz sinusoidal noise ? ?70 ? dbc table 9. ac characteristics (continued) (v dd =1.8v ?? 5% , 2.5 v ? 5%, or 3.3 v ?? 10%,t a = ?40 to 85 ? c ) parameter symbol test condition min typ max unit notes: 1. for clock division applications, a minimum input clock slew rate of 30 mv/ns is required. 2. see figure 4. 3. defined as skew between outputs on different devices operati ng at the same supply voltages, temperatures, and equal load conditions. using the same type of inputs on each devi ce, the outputs are measured at the differential cross points. 4. measured for 156.25 mhz carrier frequency. sine-wave noise added to v ddox (1.8v=50mv pp , 2.5/3.3v=100mv pp ) and noise spur amplitude measured. see an491 for further details.
SI53303 preliminary rev. 0.4 9 table 10. thermal conditions parameter symbol test condition value unit thermal resistance, junction to ambient ? ja still air 46.2 c/w thermal resistance, junction to case ? jc still air 27.1 c/w table 11. absolute maximum ratings parameter symbol test condition min typ max unit storage temperature t s ?55 ? 150 ? c supply voltage vdd ?0.5 ? 3.8 v input voltage v in ?0.5 ? vdd+ 0.3 v output voltage v out ??vdd+ 0.3 v esd sensitivity hbm hbm, 100 pf, 1.5 k ? 2000 ? ? v esd sensitivity cdm 500 ? ? v peak soldering reflow temperature t peak pb-free; solder reflow profile per jedec j-std-020 ? ? 260 ? c maximum junction temperature t j ? ? 125 ? c note: stresses beyond those listed in this table may caus e permanent damage to the device. functional operation specification compliance is not implied at these conditi ons. exposure to maximum rating conditions for extended periods may affect device reliability.
SI53303 10 preliminary rev. 0.4 2. functional description the SI53303 is a low jitter, low skew dual 1:5 differenti al output buffer. the device has a universal input that accepts most common differential or lvcmos input signals. each output bank features control pins to select signal format, output enable, output divider setting and lvcmos drive strength. 2.1. universal, any-format input the SI53303 has a universal input stage that enables simple interfacing to a wide variety of clock formats, including lvpecl, lvcmos, lvds, hcsl, and cml. tables 12 and 13 summa rize the various inpu t ac- and dc -coupling options supported by the device. figures 3 and 4 show the recommend ed input clock termination options. figure 1. differential lvpecl, lvds, cml ac-coupled input termination figure 2. lvcmos dc-coupled input termination table 12. lvpecl, lvcmos, and lvds lvpecl lvcmos lvds ac-couple dc-couple ac-couple d c-couple ac-couple dc-couple 1.8 v n/a n/a no yes yes no 2.5/3.3 v yes yes no yes yes yes table 13. hcsl and cml hcsl cml ac-couple dc-couple ac-couple dc-couple 1.8 v no no yes no 2.5/3.3 v no yes (3.3 v) yes no si533xx 0.1 uf 0.1 uf clkx /clkx 100 v dd si533xx v ref clkx /clkx 50 = 3.3v, 2.5v, 1.8v v ddo rs cmos driver 0.1 uf n ote: v ddo and v dd must be at the same voltage level.
SI53303 preliminary rev. 0.4 11 figure 3. differential dc-coupled input terminations v dd si533xx r 1 v ddo r 2 r 1 r 2 ?standard? lvpecl driver v term = v ddo ? 2v r 1 // r 2 = 50 ohm clkx = 3.3v or 2.5v v ddo 3.3v lvpecl: r 1 = 127 ohm, r 2 = 82.5 ohm 2.5v lvpecl: r 1 = 250 ohm, r 2 = 62.5 ohm dc coupled lvpecl termination scheme 1 /clkx 50 50 v dd si533xx 50 50 v term = v ddo ? 2v = 3.3v or 2.5v v ddo 50 50 ?standard? lvpecl driver clkx /clkx dc coupled lvpecl termination scheme 2 v dd si533xx 50 50 dc coupled lvds termination = 3.3v or 2.5v v ddo 100 standard lvds driver clkx /clkx v dd si533xx 50 50 dc coupled hcsl termination scheme = 3.3v v ddo standard hcsl driver 50 50 33 33 clkx /clkx note: 33 ohm series termination is optional depending on the location of the receiver.
SI53303 12 preliminary rev. 0.4 2.2. input bias resistors internal bias resistors ensure a differential output low co ndition in the event that the clock inputs are not connected. the noninverting input is biased with a 18.75 k ? pulldown to gnd and a 75 k ? pullup to v dd . the inverting input is biased with a 75 k ? pullup to v dd . figure 4. input bias resistors 2.3. universal, an y-format output buffer the SI53303 has highly fl exible output drivers that support a wide rang e of clock signal formats, including lvpecl, low power lvpecl, lvds, cml, hcsl, and lvcmos. sfouta[1] and sfoutb[1] are 3-level inputs that can be pin-strapped to select the bank a and bank b clock signal formats, respectively. this feature enables the device to be used for level translation in addition to clock distribution, minimizing the number of unique buffer part numbers required in a typical application and simplifying design reuse. for emi reduction applications, four lvcmos drive strength options are available for each v ddo setting. table 14. output signal format selection sfoutx[1] sfoutx[0] v ddo x =3.3v v ddo x =2.5v v ddo x =1.8v open* open* lvpecl lvpecl n/a 0 0 lvds lvds lvds 0 1 lvcmos, 24ma drive lvcmos, 18ma drive lvcmos, 12ma drive 1 0 lvcmos, 18ma drive lvcmos, 12ma drive lvcmos, 9ma drive 1 1 lvcmos, 12ma drive lvcmos, 9ma drive lvcmos, 6ma drive open* 0 lvcmos, 6ma drive lvcmos, 4ma drive lvcmos, 2ma drive open* 1 lvpecl low power lvpecl low power n/a 0 open* cml cml cml 1 open* hcsl hcsl hcsl *note: sfoutx[1:0] are 3-level input pins. tie low for ?0? setting. tie high for ?1? setting. when left open, the pin floats to v dd /2. r pu clk0 or clk1 r pu r pu = 75 kohm r pd = 18.75 kohm r pd + ? v dd
SI53303 preliminary rev. 0.4 13 2.4. synchronous output enable the SI53303 features a synchronous output enable (disable ) feature. output enable is sampled and synchronized on the falling edge of the input clock. this feature prevents runt pulses from being generated when the outputs are enabled or disabled. figure 5. synchronous output enable when oe is low, q is held low and q is held high for differential output formats. for lvcmos output format options, both q and q are held low when oe is set low. the device outputs are enabled when the output enable pin is unconnected. clkin q q = in disabled oe note 1. outputs are disabled after 1 to 2 negative edges of the input clock.
SI53303 14 preliminary rev. 0.4 2.5. flexible output divider the SI53303 provides optional clock division in additio n to clock distribution. the divider setting for each bank of output clocks is selected via 3-level c ontrol pins as shown in the table below. leaving the divx pi ns open will force a divider value of 1 which is the default mode of operation. 2.6. output enable logic each 1:5 output has an independent clock input (clk 0/clk1) and an output enable pin. the table below summarizes the input and output clock based upon the state of the input clock and the oe pin. 2.7. power supply (v dd and v ddo x ) the device includes separate core (v dd ) and output driver supplies (v ddox ). this feature allows the core to operate at a lower voltage than v ddo , reducing current consumption in mixed supply applications. the core v dd supports 3.3v, 2.5v, or 1.8v. each output bank has its own v ddox supply, supporting 3.3v, 2.5v, or 1.8v. table 15. divider selection divx divider value open* ? 1 (default) 0 ? 2 1 ? 4 *note: divx are 3-level input pins. tie low for ?0? setting. tie high for ?1? setting. when left open, the pin floats to v dd /2. table 16. input clock and output enable logic clk oe 1 q 2 lh l hh h xll 3 notes: 1. output enable active high 2. on the next negative transition of clk0 or clk1. 3. single-end: q=low, q =high differential: q=low, q =high
SI53303 preliminary rev. 0.4 15 2.8. output clo ck termination options the recommended output clock termination options are show n below. unused output clocks should be left floating. figure 6. lvpecl output termination si533xx r 1 v ddo r 2 r 1 r 2 50 50 lvpecl receiver v term = v ddo ? 2v r 1 // r 2 = 50 ohm q qn = 3.3v or 2.5v v ddo 3.3v lvpecl: r 1 = 127 ohm, r 2 = 82.5 ohm 2.5v lvpecl: r 1 = 250 ohm, r 2 = 62.5 ohm dc coupled lvpecl termination scheme 1 v dd = v ddo si533xx 50 50 lvpecl receiver v term = v ddo ? 2v q qn = 3.3v or 2.5v v ddo 50 50 v dd = v ddo dc coupled lvpecl termination scheme 2 si533xx r 1 v ddo r 2 r 1 r 2 50 50 v bias = v dd ? 1.3v r 1 // r 2 = 50 ohm rb rb 0.1 uf ac coupled lvpecl termination scheme 1 q qn 0.1 uf = 3.3v or 2.5v v ddo lvpecl receiver = 3.3v or 2.5v v dd 3.3v lvpecl: r 1 = 82.5 ohm, r 2 = 127 ohm, rb = 120 ohm 2.5v lvpecl: r 1 = 62.5 ohm, r 2 = 250 ohm, rb = 90 ohm si533xx 50 50 rb rb 0.1 uf ac coupled lvpecl termination scheme 2 q qn 0.1 uf = 3.3v or 2.5v v ddo lvpecl receiver = 3.3v or 2.5v v dd 50 50 3.3v lvpecl: rb = 120 ohm 2.5v lvpecl: rb = 90 ohm
SI53303 16 preliminary rev. 0.4 figure 7. lvds, cml, and hcsl output termination 50 50 0.1 uf ac coupled lvds termination 0.1 uf v dd 50 50 si533xx q qn = 3.3v or 2.5v or 1.8v v ddo lvds receiver 50 50 dc coupled hcsl source termination v dd standard hcsl receiver 86.6 86.6 42.2 42.2 si533xx q qn = 3.3v v ddo 50 50 0.1 uf ac coupled cml termination 0.1 uf v dd 100 si533xx q qn = 3.3v or 2.5v or 1.8v v ddo cml receiver 50 50 dc coupled hcsl receiver termination v dd standard hcsl receiver 50 50 si533xx q qn = 3.3v v ddo 50 50 dc coupled lvds and low-power lvpecl termination v dd 100 lvds receiver si533xx q qn = 3.3v or 2.5v or 1.8v v ddo
SI53303 preliminary rev. 0.4 17 figure 8. lvcmos output termination table 17. recommended lvcmos r s series termination sfoutx[1] sfoutx[0] r s (ohms) 3.3v 2.5v 1.8v 0 1 33 33 33 1 0 33 33 33 11000 open0000 50 rs si533xx cmos driver zout c l = 15 pf cmos receivers zo
SI53303 18 preliminary rev. 0.4 2.9. ac timing waveforms figure 9. ac waveforms q n q m t sk t sk t plh t r t f q q clk q t phl output-output skew propagation delay rise/fall time vpp/2 vpp/2 vpp/2 vpp/2 20% vpp 80% vpp 80% vpp 20% vpp
SI53303 preliminary rev. 0.4 19 2.10. typical phase noise performance figure 10. SI53303 phase noise note: measured single-endedly. source jitter 39.34fs @156.25mhz 30.26fs @312.5mhz 22.77fs @625mhz total jitter 55.00fs @625mhz 106.37fs @312.5mhz 191.58fs @156.25mhz
SI53303 20 preliminary rev. 0.4 2.11. input noise isolation figure 11. input noise isolation table 18. SI53303 additive jitter frequency (mhz) source jitter (fs) total jitter (fs) additive jitter (fs) 156.25 39.34 191.58 187.50 312.5 30.26 106.37 101.98 625 22.77 55.00 50.07
SI53303 preliminary rev. 0.4 21 2.12. power supply noise rejection the device supports on-chip supply voltage regulation to reject noise present on the power supply, simplifying low jitter operation in real-world environments. this feat ure enables robust operation alongside fpgas, asics and socs and may reduce board-level filtering requirements. for more information, see an491: power supply rejection for low jitter clocks. figure 12. power supply noise rejection (100 mvpp sinusoidal power supply noise applied) b c) )f 0+] a mplitude (d b spur a
SI53303 22 preliminary rev. 0.4 3. pin description: 44-pin qfn table 19. pin description pin # name description 1 diva output divider control pin for bank a three-level input control. inte rnally biased at vdd/2. can be left floating or tied to ground or v dd . 2 sfouta[1] output signal format control pin for bank a three-level input control. inte rnally biased at vdd/2. can be left floating or tied to ground or v dd . 3 sfouta[0] output signal format control pin for bank a three-level input control. inte rnally biased at vdd/2. can be left floating or tied to ground or v dd . 4q2 output clock 2 (complement) 5 q2 output clock 2 6 gnd ground 7q1 output clock 1 (complement) 8 q1 output clock 1 gnd pad 27 26 25 24 23 29 28 30 32 31 33 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 7 8 9 10 11 5 6 4 2 3 1 nc nc nc clk0 clk0 clk1 clk1 v ref v ddoa q0 q0 q1 q1 q2 q2 q3 q3 q4 q4 gnd v ddob q5 oea q5 q6 q6 q7 q7 q8 q8 q9 q9 gnd diva sfouta[1] sfouta[0] oeb divb sfoutb[1] sfoutb[0] gnd v dd nc nc
SI53303 preliminary rev. 0.4 23 9q0 output clock 0 (complement) 10 q0 output clock 0 11 nc no connect 12 vdd core voltage supply bypass with 1.0 f capacitor and plac e close to the vdd pin as possible 13 nc no connect 14 clk0 input clock 0 15 clk0 input clock 0 (complement) when clk0 is driven by a single-end input, connect v ref to clk0 clk0 contains an internal pull-up resistor 16 oea output enable?bank a when oe = high, the bank a outputs are enabled when oe = low, q is held low and q is held high for differential formats for lvcmos, both q and q are held low when oe is set low oea contains an internal pull-up resistor 17 v ref input reference voltage when driven by a lvcmos clock input, connect the unused clock input to v ref and a 0.1f cap to ground. when driven by a differential clock, do not connect the v ref pin. 18 oeb output enable?bank b when oe = high, the bank b outputs are enabled when oe = low, q is held low and q is held high for differential formats for lvcmos, both q and q are held low when oe is set low oeb contains an internal pull-up resistor. 19 clk1 input clock 1 20 clk1 input clock 1 (complement) when clk1 is driven by a single-end input, connect v ref to clk1 clk1 contains an internal pull-up resistor 21 nc no connect 22 gnd ground 23 nc no connect 24 q9 output clock 9 (complement) 25 q9 output clock 9 26 q8 output clock 8 (complement) 27 q8 output clock 8 28 nc no connect table 19. pin description (continued) pin # name description
SI53303 24 preliminary rev. 0.4 29 q7 output clock 7 (complement) 30 q7 output clock 7 31 sfoutb[0] output signal format control pin for bank b three-level input control. inte rnally biased at vdd/2. can be left floating or tied to ground or v dd . 32 sfoutb[1] output signal format control pin for bank b three-level input control. inte rnally biased at vdd/2. can be left floating or tied to ground or v dd . 33 divb output divider configuration bit for bank b three-level input control. inte rnally biased at vdd/2. can be left floating or tied to ground or v dd . 34 v ddo b output clock voltage supply?bank b (outputs: q5 to q9) bypass with 1.0 f capacitor and place close to the v ddo b pin as possible 35 q6 output clock 6 (complement) 36 q6 output clock 6 37 q5 output clock 5 (complement) 38 q5 output clock 5. 39 gnd ground. 40 q4 output clock 4 (complement) 41 q4 output clock 4. 42 q3 output clock 3 (complement) 43 q3 output clock 3 44 v ddoa output voltage supply?bank a (outputs: q0 to q4) bypass with 1.0 f capacitor and place close to the v ddoa pin as possible gnd pad gnd ground pad power supply ground and thermal relief table 19. pin description (continued) pin # name description
SI53303 preliminary rev. 0.4 25 4. ordering guide part number package pb-free, rohs-6 temperature SI53303-b-gm 44-qfn yes ?40 to 85 ? c
SI53303 26 preliminary rev. 0.4 5. package outline 5.1. 7x7 mm 44-qfn package diagram figure 13. SI53303 7x7 mm 44-qfn package diagram ?
SI53303 preliminary rev. 0.4 27 table 20. package diagram dimensions dimension min nom max a 0.800.850.90 a1 0.00 0.02 0.05 b 0.180.250.30 d 7.00 bsc d2 2.65 2.80 2.95 e 0.50 bsc e 7.00 bsc e2 2.65 2.80 2.95 l 0.300.400.50 aaa ? ? 0.10 bbb ? ? 0.10 ccc ? ? 0.08 ddd ? ? 0.10 notes: 1. all dimensions shown are in milli meters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jedec solid state outline mo-220. 4. recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components.
SI53303 28 preliminary rev. 0.4 6. pcb land pattern 6.1. 7x7 mm 44-qfn package land pattern figure 14. SI53303 7x7 mm 44-qfn package land pattern table 21. pcb land pattern dimension min max dimension min max c1 6.80 6.90 x2 2.85 2.95 c2 6.80 6.90 y1 0.75 0.85 e 0.50 bsc y2 2.85 2.95 x1 0.20 0.30 notes: general 1. all dimensions shown are in mil limeters (mm) unless otherwise noted. 2. this land pattern design is based on the ipc-7351 guidelines. solder mask design 1. all metal pads are to be non-solder mask defined (nsmd). cl earance between the solder mask and the metal pad is to be 60 ? m minimum, all the way around the pad. stencil design 1. a stainless steel, laser-cut and electro-pol ished stencil with trapezoidal walls should be used to assure good solder paste release. 2. the stencil thickness should be 0.125 mm (5 mils). 3. the ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. 4. a 2x2 array of 1.0 mm square openings on 1.45 mm pi tch should be used for the center ground pad. card assembly 1. a no-clean, type-3 solder paste is recommended. 2. the recommended card reflow profile is per the jedec/ ipc j-std-020 specification for small body components. ?
SI53303 preliminary rev. 0.4 29 7. top marking 7.1. SI53303 top marking 7.2. top marking explanation mark method: laser font size: 1.9 point (26 mils) right-justified line 1 marking: device part number 53303-b-gm line 2 marking: yy = year ww = work week assigned by assembly supplier. corresponds to the year and work week of the mold date. tttttt = mfg code manufacturing code from the assembly purchase order form. line 3 marking: circle = 1.3 mm diameter center-justified ?e3? pb-free symbol country of origin iso code abbreviation tw line 4 marking circle = 0.75 mm diameter filled pin 1 identification ?
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